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Features
* PC603eTM Microprocessor (Embedded PowerPCTM Core) at 100 - 200 MHz
- 140 MIPS at 100 MHz (Dhrystone 2.1) - 280 MIPS at 200 MHz (Dhrystone 2.1) - High-performance, Superscalar Microprocessor - Disable CPU Mode - Improved Low-power Core - 16-Kbyte Data and 16-Kbyte Instruction Cache, Four-way Set Associative - Memory Management Unit - No Floating Point Unit - Common On-chip Processor (COP) System Integration Unit (SIU) - Memory Controller, Including Two Dedicated SDRAM Machines - PCI up to 66 MHz (Available in Subsequent Versions) - Hardware Bus Monitor and Software Watchdog Timer - IEEE 1149.1 JTAG Test Access Port High-performance Communications Processor Module (CPM) with Operating Frequency up to 166 MHz - PowerPC and CPM May Run at Different Frequencies - Supports Serial Bit Rates up to 710 Mbps at 133 MHz - Parallel I/O Registers - On-board 24 KBytes of Dual-port RAM - Two Multi-channel Controllers (MCCs) Each Supporting 128 Full-duplex, 64-Kbps, HDLC Lines - Virtual DMA Functionality Two Bus Architectures: One 64-bit PowerPC and One 32-bit Local Bus (or PCI on PC8265) Two UTOPIA Level-2 Master/Slave Ports, Both with Multi-PHY Support. One Can Support 8/16 bit Data Three MIL Interfaces Eight TDM Interfaces (T1/E1), Two TDM Ports Can Be Glueless to T3/E3 Power Consumption: 2.5W at 133 MHz
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PowerPC-based Communications Processors PC8260 PowerQUICC IITM
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Description
The PC8260 PowerQUICC IITM is a versatile communications processor that integrates on one chip, a high-performance PowerPC (PC603e) RISC microprocessor, a highly flexible system integration unit, and many communications peripheral controllers that can be used in a variety of applications, particularly in communications and networking systems. The core is an embedded variant of the PC603e microprocessor, specifically referred to later in this document as the EC603e, with 16 Kbytes of instruction cache and 16 Kbytes of data cache and no floating-point unit (FPU). The system interface unit (SIU) consists of a flexible memory controller that interfaces to almost any user-defined memory system, a 60x-to-PCI bus bridge (available in future revisions) and many other peripherals, making this device a complete system on a chip. The communications processor module (CPM) includes all the peripherals found in the PC860, with the addition of three high-performance communication channels that support new emerging protocols (for example, 155-Mbps ATM and Fast Ethernet). Equipped with dedicated hardware, the PC8260 can handle up to 256 full-duplex, time-division, multiplexed logical channels.
Rev. 2131A-08/01
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Screening Quality Packaging
This product is manufactured in full compliance with: * * * * Upscreening based upon Atmel standards. Full military temperature range (TJ = -55C, TJ = +125C) Industrial temperature range (TJ = -40C, TJ = +110C) Core power supply: 2.5V 5% (L-Spec for 200 MHz) 2.50V to 2.75V (R-Spec for 250 MHz) (tbc) * * I/O power supply: 3.0V to 3.6V 480-ball Tape Ball Grid Array package (TBGA 37.5 mm x 37.5 mm)
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PC8260 Architecture General Overview
The PC8260 has two external buses to accommodate bandwidth requirements from the highspeed system core and the very fast communications channels. The device is composed of the following three major functional blocks: * * * A 64-bit PowerPC core derived from the EC603e with MMUs and caches. A system interface unit (SIU). A communications processor module (CPM). Both the system core and the CPM have an internal PLL, which allows independent optimization of the frequencies at which they run. The system core and CPM are both connected to the 60x bus.
Figure 1. PC8260 Block Diagram
16-Kbyte Instruction Cache 60x Bus IMMU EC603e PowerPC Core 16-Kbyte Data Cache DMMU Memory Controller 60x-to-PCI Bus Bridge (PC8265 only) 60x-to-Local Bus Bridge PCI/ Local Bus
Timers Parallel I/O Baud Rate Generator
Interrupt Controller
24-Kbyte DualPort RAM
Bus Interface Unit Serial DMAs Clock Counter 4 Virtual IDMAs
32-Bit RISC Communications Processor (CP) and Program ROM
System Functions
MCC
MCC
FCC
FCC
FCC
SCC
SCC
SCC
SCC
SMC
SMC
SPI
I 2C
Time Slot Assigner
Serial Interface 2 UTOPIA 8 TDMs 3 Mlls Non-Multiplexed I/O
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EC603e Core
The EC603e core is derived from the PowerPC603e microprocessor without the floating-point unit and with power management modifications.The core is a high-performance low-power implementation of the PowerPC family of reduced instruction set computer (RISC) microprocessors. The EC603e core implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8, 16 and 32 bits. The EC603e cache provides snooping to ensure data coherency with other masters. This helps ensure coherency between the CPM and system core. The core includes 16 Kbytes of instruction cache and 16 Kbytes of data cache. It has a 64-bit split-transaction external data bus which is connected directly to the external PC8260 pins. The EC603e core has an internal common on-chip (COP) debug processor. This processor allows access to internal scan chains for debugging purposes. It is also used as a serial connection to the core for emulator support. The EC603e core performance for the SPEC 95 benchmark for integer operations ranges between 4.4 and 5.1 at 200 MHz. In Dhrystone 2.1 MIPS, the EC603e is 280 MIPS at 200 MHz (compared to 86 MIPS of the PC860 at 66 MHz). The EC603e core can be disabled. In this mode, the PC8260 functions as a slave peripheral to an external core or to another PC8260 device with its core enabled.
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System Interface Unit (SIU)
The SIU consists of the following: * A 60x-compatible parallel system bus configurable to 64-bit data width. The PC8260 supports 64-, 32-, 16-, and 8-bit port sizes.The PC8260 internal arbiter arbitrates between internal components that can access the bus (system core, PCI bridge, CPM, and one external master). This arbiter can be disabled, and an external arbiter can be used if necessary. A local (32-bit data, 32-bit internal and 18-bit external address) bus. This bus is used to enhance the operation of the very high-speed communication controllers. Without requiring extensive manipulation by the core, the bus can be used to store connection tables for ATM or buffer descriptors (BDs) for the communication channels or raw data that is transmitted between channels. The local bus is synchronous to the 60x bus and runs at the same frequency. The local bus can be configured as a 32-bit data and up to 66 MHz PCI (version 2.1) bus. In PCI mode the bus can be programmed as a host or as an agent. The PCI bus can be configured to run synchronously or asynchronously to the 60x bus. The PC8260 has an internal PCI bridge with an efficient 60x-to-PCI DMA for memory block transfers. Applications that require both the local bus and PCI bus need to connect an external PCI bridge. A memory controller supporting 12 memory banks that can be allocated for either the system or the local bus. The memory controller is an enhanced version of the PC8260 memory controller. It supports three user-programmable machines. Besides supporting all PC8260 features, the memory controller also supports SDRAM with page mode and address data pipeline Supports JTAG controller IEEE 1149.1 test access port (TAP). A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt timer, and other system functions useful in embedded applications. Glueless interface to L2 cache and 4-/16-K-entry CAM.
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Communication Processor Module (CPM)
The CPM contains features that allow the PC8260 to excel in a variety of applications targeted mainly for networking and telecommunication markets. The CPM is a superset of the PC8260 PowerQUICC CPM, with enhancements on the CP performance and additional hardware and microcode routines that support high bit rate protocols like ATM (up to 155 Mbps full-duplex) and Fast Ethernet (100 Mbps full-duplex). The following list summarizes the major features of the CPM: * The communications processor (CP) is an embedded 32-bit RISC controller residing on a separate bus (CPM local bus) from the 60x bus (used by the system core). With this separate bus, the CP does not affect the performance of the PowerPC core. The CP handles the lower layer tasks and DMA control activities, leaving the PowerPC core free to handle higher layer activities. The CP has an instruction set optimized for communications, but can also be used for general-purpose applications, relieving the system core of small often repeated tasks. Two serial DMAs (SDMAs) that can do simultaneous transfers, optimized for burst transfers to the 60x bus and to the local bus. Three full-duplex, serial fast communications controllers (FCCs) supporting ATM (155 Mbps) protocol through UTOPIA2 interface (there are two UTOPIA interfaces on the PC8260), IEEE 802.3 and Fast Ethernet protocols, HDLC up to E3 rates (45 Mbps) and totally transparent operation. Each FCC can be configured to transmit fully transparent and receive HDLC, or vice-versa. Two multichannel controllers (MCCs) that can handle an aggregate of 256 x 64 Kbps HDLC or transparent channels, multiplexed on up to eight TDM interfaces. The MCC also supports super-channels of rates higher than 64 Kbps and subchanneling of the 64-Kbps channels. Four full-duplex serial communications controllers (SCCs) supporting IEEE802.3/Ethernet, high-level synchronous data link control, HDLC, local talk, UART, synchronous UART, BISYNC and transparent. Two full-duplex serial management controllers (SMC) supporting GCI, UART, and transparent operations. Serial peripheral interface (SPI) and I2C bus controllers. Time-slot assigner (TSA) that supports multiplexing of data from any of the four SCCs, three FCCs, and two SMCs.
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Software Compatibility Issues
As much as possible, the PC8260 CPM features were made similar to those of the previous devices (PC860). The code ports easily from previous devices to the PC8260, except for new protocols supported by the PC8260. Although many registers are new, most registers retain the old status and event bits, so an understanding of the programming models of the 68360, PC860, or PC850 is helpful. Note that the PC8260 initialization code requires changes from the PC8260 initialization code.
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Differences Between PC860 and PC8260
The following PC860 features are not included in the PC8260: * * * * * * * * * * * * * * * On-chip crystal oscillators (must use external oscillator) 4 MHz oscillator (input clock must be at the bus speed) Low power (standby) modes Battery-backup real-time clock (must use external battery-backup clock) BDM (COP offers most of the same functionality) True little endian mode (except the PCI bus) PCMCIA interface Infrared (IR) port QMC protocol in SCC (256 HDLC channels are supported by the MCCs) Multiply and accumulate (MAC) block in the CPM Centronics port (PIP) Asynchronous HDLC protocol (optional RAM microcode) Pulse-width modulated outputs SCC Ethernet controller option to sample 1 byte from the parallel port when a receive frame is complete. Parallel CAM interface for SCC (Ethernet)
Serial Protocol Table
Table 1 summarizes available protocols for each serial port. Table 1. PC8260 Serial Protocols
Port Protocol ATM (Utopia) 100BaseT 10BaseT HDLC HDLC_BUS Transparent UART DPLL Multichannel x FCC x x x x x x x x x x x x x x x SCC MCC SMC
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Pin Assignment
Table 2 shows the pinout of the PC8260. Table 2. Pinout
Pin Name BR BG ABB/IRQ2 TS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 Ball W5 F4 E2 E3 G1 H5 H2 H1 J5 J4 J3 J2 J1 K4 K3 K2 K1 L5 L4 L3 L2 L1 M5 N5 N4 N3 N2 N1 P4 P3 P2 P1 R1 R3 R5
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Table 2. Pinout (Continued)
Pin Name A31 TTO TT1 TT2 TT3 TT4 TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG DBB/IRQ3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 Ball R4 F1 G4 G3 G2 F2 D3 C1 E4 D2 F5 F3 E1 V1 V2 B20 A18 A16 A13 E12 D9 A6 B5 A20 E17 B15 B13 A11 E9 B7 B4 D19 D17 D15 C13 B11
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Table 2. Pinout (Continued)
Pin Name D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 Ball A8 A5 C5 C19 C17 C15 D13 C11 B8 A4 E6 E18 B17 A15 A12 D11 C8 E7 A3 D18 A187 A14 B12 A10 D8 B6 C4 C18 E16 B14 C12 B10 A7 C6 D5 B18
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Table 2. Pinout (Continued)
Pin Name D57 D58 D59 D60 D61 D62 D63 DPO/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT DBG2 IRQ3/DP3/CKSTP_OUT/EXT BR3 IRQ4/DP4/CORE_SRESET/EXT BG3 IRQ5/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSEO IRQ7/DP7/CSE1 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10/BCTL1 Ball B16 E14 D12 C10 E8 D6 C2 B22 A22 E21 D21 C21 B21 A21 E20 V3 C22 V5 W1 U2 U3 Y4 U4 R2 Y3 F25 C29 E27 E28 F26 F27 F28 G25 D29 E29 F29
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Table 2. Pinout (Continued)
Pin Name CS11/APO BADDR27 BADDR28 ALE BCTL0 PWE0/PSDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGL0 PSDWE/PGPL1 POE/OSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE0/LSDDQM0/LBS0 LWE1/LSDDQM1/LBS1 LWE2/LSDDQM2/LBS2 LWE3/LSDDQM3/LBS3 LSDA10/LGPL0 LSDWE/LGPL1 LOE/LSDRAS/LGPL2 LSDCAS/LGPL3 LGTA/LUPMWAIT/LGPL4/LPBS LGPL5 LWR L A14 L A15/SMI L A16 L A17/CKSTP_OUT L A18 L A19 Ball G28 T5 U1 T2 A27 C25 E24 D24 C24 B26 A26 B25 A25 E23 B24 A24 B23 A23 D22 H28 H27 H26 G29 D27 C28 E26 D25 C26 B27 D28 N27 T29 R27 R26 R29 R28
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Table 2. Pinout (Continued)
Pin Name L A20 L A21 L A22 L A23 L A24 L A25 L A26 L A27 L A28/CORE_SRESET L A29 L A30 L A31 LCL D0 LCL D1 LCL D2 LCL D3 LCL D4 LCL D5 LCL D6 LCL D7 LCL D8 LCL D9 LCL D10 LCL D11 LCL D12 LCL D13 LCL D14 LCL D15 LCL D16 LCL D17 LCL D18 LCL D19 LCL D20 LCL D21 LCL D22 LCL D23 Ball W20 P28 N26 AA27 P29 AA26 N25 AA25 AB29 AB28 P25 AB27 H29 J29 J28 J27 J26 J25 K25 L29 L27 L26 L25 M29 M28 M27 M26 N29 T25 U27 U26 U25 V29 V28 V27 V26
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Table 2. Pinout (Continued)
Pin Name LCL_D24 LCL_D25 LCL_D26 LCL_D27 LCL_D28 LCL_D29 LCL_D30 LCL_D31 LCL_DP0 LCL_DP1 LCL_DP2 LCL_DP3 IRQ0/NMI_OUT IRQ7INT_OUT/APE TRST TCK TMS TDI TDO TRIS PORESET HRESET SRESET QREQ RSTCONF MODCK1/AP1/TC0/BNKSEL0 MODCK2/AP2/TC1/BNKSEL1 MODCK3/AP3/TC2/BNKSEL2 XFC CLKIN PA0/RESTART1/DREQ/FCC2_UTM_TXADDRS PA1/REJECT1/FCC2_UTM_TXADDR1/DONE3 PA2/CLK20/FCC2_UTM_TXADDR0/DACK3 PA3/CLK19/FCC2_UTM_RXADDR0/DACK4/L1RXD1A2 PA4/REJECT2/FCC2/RXADDR1/DONE4 PA5/RESTART2/DREQ4/FCC2_UTM RXADDR2 Ball W27 W26 W25 Y29 Y28 Y25 AA29 AA28 L28 N28 T28 W28 W28 D1 AH3 AG5 AJ3 AE6 AF5 AB4 AG6 AH5 AF6 AA3 AJ4 W2 W3 W4 AB2 AH4 AC29 AC25 AE28 AG29 AG28 AG26
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Table 2. Pinout (Continued)
Pin Name PA6/L1RSYNCA1 PA7/SMSYN2/L1TSYNCA1/L1GNTA1 PA8/SMRSXD2/L1RXD0A1/L1RXDA1 PA6/L1RSYNCA1 PA7/SMSYN2/L1TSYNCA1/L1GNTA1 PA8/SMRXD2/L1RXD0A1/L1RXDA1 PA9/SMTXD2/L1TXD0A1 PA10/FCC1_UT8_RXD0/FCC1_UT16_RXD8/MSNUM5 PA11/FCC1_UT8_RXD1/FCC1_UT16_RXD9/MSNUM4 PA12/FCC1_UT8_RXD2/FCC1_UT16_RXD10/MSNUM3 PA13/FCC1_UT8_RXD3/FCC1_UT16_RXD11/MSNUM2 PA14/FCC1_UT8_RXD4/FCC1_UT16_RXD12/FCC1_RXD3 PA15/FCC1_UT8_RXD5/FCC1_UT16_RXD13/FCC1_RXD2 PA16/FCC1_UT8_RXD6/FCC1_UT16_RXD14/FCC1_RXD1 PA17/FCC1_UT8_RXD7/FCC1_UT16_RXD15/FCC1_RXD0/FCC1_RXD PA18/FCC1_UT8_TXD7/FCC1_UT16_TXD15/FCC1_TXD0/FCC1_TXD PA19/FCC1_UT8_TXD6/FCC1_UT16_TXD14/FCC1_TXD1 PA20/FCC1_UT8_TXD5/FCC1_UT16_TXD13/FCC1_TXD2 PA21/FCC1_UT8_TXD4/FCC1_UT16_TXD12/FCC1_TXD3 PA22/FCC1_UT8_TXD3/FCC1_UT16_TXD11 PA23/FCC1_UT8_TXD2/FCC1_UT16_TXD10 PA24/FCC1_UT8_TXD1/FCC1_UT16_TXD9/MSNUM1 PA25/FCC1_UT8_TXD0/FCC1_UT16_TXD8/MSNUM0 PA26/FCC1_UTM_RXCLAV/FCC1_UTS_RXCLAV/FCC1_MII_RX_ER PA27/FCC1_UT_RXSOC/FCC1_MII_RX DV PA28/FCC1_UTM_RXENB/FCC1_UTS_RXENB/FCC1_MII_TX_EN PA29/FCC1_UT_TXSOC/FCC1_MII_TX_ER PA30/FCC1_UTM_TXCLAV/FCC1_UTS_TXCLAV/FCC1_MII_CRS/FCC1_RTS PA31/FCC1_UTM_TXENB/FCC1_UTS_TXENB/FCC1_MII_COL PB4/FCC3_TXD3/FCC2_UT8_RXD0/L1RSYNCA2/FCC3_RTS PB5/FCC3_TXD2/FCC2_UT8_RXD1/L1TSYNCA2/L1GNTA2 PB6/FCC3_TXD1/FCC2_UT8_RXD2/L1RXDA2/L1RXD0A2 PB7/FCC3_TXD0/FCC3_TXD/FCC2_UT8_RXD3/L1TXDA2/L1TXD0A2 PB8/FCC2_UT8_TXD3/FCC3_RXD0/FCC3 RXD/TXD3/L1RSYNCD1 PB9/FCC2_UT8_TXD2/FCC3_RXD1/L1TXD2A2/L1TSYNCD1/L1GNTD1 PB10/FCC2_UT8_TXD1/FCC3_RXD2/L1RXDD1 Ball AE24 AH25 AF23 AE24 AH25 AF23 AH23 AE22 AH22 AJ21 AH20 AG19 AF18 AF17 AE16 AJ16 AG15 AJ13 AE13 AF12 AG11 AH9 AJ8 AH7 AF7 AD5 AF1 AD3 AB5 AD28 AD26 AD25 AE26 AH27 AG24 AH24
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Table 2. Pinout (Continued)
Pin Name PB11/FCC3_RXD3/FCC2_UT8_TXD0/L1TXDD1 PB12/FCC3_MII_CRS/L1CLKOB1/L1RSYNCC1/TXD2 PB13/FCC3_MII_COL/L1RQB1/L1TSYNCC1/L1GNTC1/L1TXD1A2 PB14/FCC3_MIL_TX_EN/RXD3/L1RXDC1 PB15/FCC3_MIL_TX_ER/RXD2/L1TXDC1 PB14/FCC3_MIL_RX_ER/L1CLKOA1/CLK18 PB17FCC3_MIL_RX_DV/L1RQA1/CLK17 PB18/FCC2_UT8_RXD4/FCC2_RXD3/L1CLKOD2/L1RXD2A2 PB19/FCC2_UT8_RXD5/FCC2_RXD2/L1RQD2/L1RXD3A2 PB20/FCC2_UT8_RXD6/FCC2 RXD1/L1RSYNCD2/L1TXD1A1 PB21/FCC2_UT8_RXD7/FCC2_RXD0/FCC2_RXD/ L1TSYNCD2/L1GNTD2/L1TXD2A1 PB22/FCC2_UT8_TXD7/FCC2_TXD0/FCC2_L1RXD1A1/L1RXDD2 PB23/FCC2_UT8_TXD6/FCC2_TXD1/L1RXD2A1/L1RXDD2 PB24/FCC2_UT8_TXD5/FCC2_TXD2/L1RXD3A1/L1RSYNCC2 PB25/FCC2_UT8_TXD4/FCC2_TXD3/L1TSYNCC2/L1GNTC2/L1TXD3A1 PB26/FCC2_MII_CRS/FCC2_UT8_TXD1/L1RXDC2 PB27/FCC2_MII_COL/FCC2_UT8_TXD0/L1TXDC2 PB28/FCC2_MII RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1 PB29/FCC2_UTM_RXCLAV/FCC2_UTS_RXCLAV/ L1RSYNCB2/FCC2_MII_TX_EN PB30/FCC2_MII_RX_DV/FCC2_UT_TXSOC/1RXDB2 PB31/FCC2_MII_TX_ER/FCC2_UT_RXSOC/L1TXDB2 PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2 PC1/DREQ2/BRGO6/L1RQA2 PC2/FCC3_CD/FCC2_UT8_TXD3/DONE2 PC3/FCC3_CTS/FCC2_UT8_TXD2/DACk2/CTS4 PC4/FCC2_UTM_RXENB/FCC2_UTS_RXENB/SI2_L1ST4/FCC2_CD PC5/FCC2_UTM_TXCLAV/FCC2_UTS_TXCLAV/SI2_L1ST3/FCC2_CTS PC6/FCC1_CD/L1CLKOC1/FCC1_UTM_RXADDR2/FCC1_UTS RXADDR2/ FCC1_UTM_RXCLAV1 PC7/FCC1_CTS/L1RQC1/ FCC1_UTM_TXADDR2/FCC1_UTS_TXADDR2/FCC1_UTM_TSCLAV1 PC8/CD4/RENA4/FCC1_UT16_TXD0/SI2_L1ST2/CTS3 PC9/CTS4/CLSN4/FCC1_UT16_TXD1/SI2_L1ST1/L1TSYNCA2/L1GNTA2 PC10/CD3/RENA3/FCC1_UT16_TXD2/SI1_L1ST4/FCC2_UT8_RXD3 PC11/CTS3/CLSN3/L1CLKOD1/L1TXD3A2/FCC2_UT8_RXD2 Ball AJ24 AG22 AH21 AG20 AF19 AJ18 AJ17 AE14 AF13 AG12 AH11 AH16 AE15 AJ9 AE9 AJ7 AH6 AE3 AE2 AC5 AC4 AB26 AD29 AE29 AE27 AF27 AF24 AJ26 AJ25 AF22 AE21 AE20 AE19
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Table 2. Pinout (Continued)
Pin Name PC12/CD2/RENA2/SI1_L1ST3/FCC1_UTM_RXADDR1/FCC1_UTS_RXADDR1 PC13/CTS2/SLSN2/L1RQD1/FCC1_UTM_TXADDR1/FCC1_UTS_TXADDR1 PC14/CD1/RENA1/FCC1_UTM_RXADDR0/FCC1_UTS_RXADDR0 PC15/CTS1/CLSN1/SMTXD2/FCC1_UTM_TXADDR0/FCC1_UTS_TXADDR0 PC16/CLK16/TIN3 PC17/CLK15/TIN4/BRGO8 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7 PC20/CLK12/TGATE1 PC21/CLK11/BTGO6 PC22/CLK10/DONE1 PC23/CLK9/BRGO5/DACK1 PC24/FCC2_UT8_TXD3/CLK8/TOUT4 PC25/FCC2_UT8_TXD2/CLK7/BRGO4 PC26/CLK6/TOUT3/TMCLK PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3 PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 PC30/FCC2_UT8_TXD3/CLK2/TOUT1 PC31/CLK1/BRGO1 PD4/BRGO8/L1TSYNCD1/L1GNTD1/FCC3_RTS/SMRXD2 PD5/FCC1_UT16_TXD3/DONE1 PD6/FCC1_UT16_TXD4/DACK1 PD7/SMSYN1/FCC1_UTM_TXADDR3/FCC1_UTS_TXADDR3/FCC1_TXCLAV2 PD8/SMRXD1/FCC2_UT_TXPRTY/BRGO5 PD9/SMTXD1/FCC2_UT_RXPRTY/BRGO3 PD10/L1CLKOB2/FCC2_UT8_RXD1/L1RSYNCB1/BRGO4 PD11/L1RQB2/FCC2_UT8_RXD0/L1TSYNCB1/L1GNTB1 PD12/SI1_L1ST2/L1RXDB1 PD13/SI1_L1ST1/L1RTDB1 PD14/FCC1_UT16_RXD0/L1CLKOC2/L2CSCL PD15/FCC1_UT16_RXD1/L1RQC2/I2CSDA PD16/FCC1_UT_TXPRTY/L1TSYNCC1/L1GNTC1/SPIMISO PD17/FCC1_UT_RXPRTY/BRGO2/SPIMOSI PD18/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/FCC1_UTM_RXCLAV3/ SPICLK Ball AE18 AH18 AH17 AG16 AF15 AJ15 AH14 AG13 AH12 AJ11 AG10 AE10 AF9 AE8 AJ6 AG2 AF3 AF2 AE1 AD1 AC28 AD27 AF29 AF28 AG25 AH26 AJ27 AJ23 AG23 AJ22 AE20 AJ20 AG18 AG17 AF16
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Table 2. Pinout (Continued)
Pin Name PD19/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/FCC1_UTM TXCLAV3/SPISEL/BRGO1 PD20/RTS4/TENA4/FCC1_UT16_RXD2/L1RSYNCA2 PD21/TXD4/FCC1_UT16_RXD3/L1RXD0A2/L1RXDA2 PD22/RXD4/FCC1_UT16_TXD5/L1TXD0A2/L1TXDA2 PD23/RTS3/TENA3/FCC1_UT16_RXD4/L1RSYNCD1 PD24/TXD3/FCC1_UT16_RXD5/L1RXDD1 PD25/RXD3/FCC1_UT16_TXD6/L1TXDD1 PD26/RTS2/TENA2/FCC1_UT16_RXD6/L1RSYNCC1 PD27/TXD2/FCC1_UT16_RXD7/L1RXDC1 PD28/RXD2/FCC1_UT16_TXD7/L1TXDC1 PD29/RTS1/TENA1/FCC1_UTM_RXADDR3/FCC1_UTS_RXADDR3/ FCC1 UTM RXCLAV2 PD30/FCC2_UTM_TXENB/FCC2_UTS_TXENB/TXD1 PD31/RXD1 VCCSYN VCCSYN1 GNDSYN THERMAL0 (thermal ball) THERMAL1 (thermal ball) SPARE1 SPARE4 SPARE5 SPARE6 Ball AH15 AJ14 AH13 AJ12 AE12 AF10 AG9 AH8 AG7 AE4 AG1 AD4 AD2 AB3 B9 AB1 AA1 AG4 AE11 UF AF25 V4
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Table 2. Pinout (Continued)
Pin Name I/O Power Ball AG21,AG14, AG8, AJ1, AJ2, AH1, AH2,AG3, AF4, AE5, AC27, Y27, T27, P27, K26, G27, AE25, AF26, AG27, AH28, AH29, AJ28, AJ29, C7,C14,C16,C2 0,C23, E10, A28, A29, B28, B29, C27, D26, E25, H3, M4, T3, AA4, A1, A2, B1, B2, C3, D4, E5 U28, U29, K28, K29, A9, A19, B19, M1, M2, Y1, Y2, AC1, AC2, AH19, AJ19, AH10, AJ10, AJ5 U28, U29, K28, K29, A9, A19, B19, M1, M2, Y1, Y2, AC1, AC2, AH19, AJ19, AH10, AJ10, AJ5 Symbol Legend:
Core Power
Ground
Note:
Overline: UTM: UTS: 2UT8: UT16: MII:
Signals with overlines, such as TA, are active low Indicates that a signal is part of the UTOPIA master interface Indicates that a signal is part of the UTOPIA slave interface Indicates that a signal is part of the 8-bit UTOPIA interface Indicates that a signal is part of the 16-bit UTOPIA interface Indicates that a signal is part of the media independent interface
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Figure 2. PowerQUICC II External Signals
VCCSYN/GNDSYN/VCCSYN1/VDDH/VDD/VSS P AR / L_A14 SMI/FRAME / L_A15 TRDY / L_A16 CKSTOP_OUT/IRDY / L_A17 STOP/ L_A18 DEVSEL / L_A19 IDSEL / L_A20 PERR / L_A21 100 1 1 1 1 1 1L 1 O 1 32 5 4 1 1 1 1 1 1 1 1 61 01 1 x1 1 B1 1 U1 S 64 1 1 1 1 1 1 1 1 1 1 1 1 1 10 1 1 2 1 M1 E8 M1 C1 1 1 1 1 1 J1 T1 A1 G1 A[0:31] TT[0:4] TSIZ[0:3] TBST GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR BR BG ABB/IRQ2 TS AACK ARTRY DBG DBB/IRQ3 D[0:63] NC/DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET /EXT_BG IRQ5/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PS_DVAL TA TEA IRQ0/NMI_OUT IRQ7/INT_OUT/APE CS[0:9] CS[10]/BCTL1/DBG_DIS CS[11]/AP[0] BADDR[27:28] ALE BCTL0 PWE[0:7]/PSDDQM[0:7]/PBS[0:7] PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 TMS TDI TCK TRST TDO
SERR / L_A22 REQ0 / L_A23 REQ1 / L_A24 GNT0 / L_A25 GNT1 / L_A26 CLK / L_A27 CORE_SRESET/RST / L_A28 INTA/ L_A29 LOCK/ L_A30 L_A31 AD[0:31]/LCL_D[0:31] C/BE[0:3] /LCL_DP[0:3] LBS[0:3]/LSDDQM [0:3]/LWE [0:3] LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LSDRAS /LOE LGPL3/LSDCAS LPBS/LGPL4/LUPWAIT/LGTA LGPL5 LWR PA[0:31] PB[4:31] PC[0:31] PD[4:31] PORESET RSTCONF HRESET SRESET QREQ XFC CLKIN TRIS BNKSEL[0]/TC[0]/AP[1]/MODCK1 BNKSEL[1]/TC[1]/AP[2]/MODCK2 BNKSEL[2]/TC[2]/AP[3]/MODCK3 TERM[0:1] NC
1 1 1B 1 U 1 1S 1 1 1 32 4 4 1 1 M 1 E 1 M 1 C 1 1 32 P 28 32 I 28 O 1 1 1 1R 1
C A 1 L
S 1T
1 1 1 1 1 2 4
C L K
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Signal Descriptions
The PowerQUICC II system bus signals consist of all the lines that interface with the external bus. Many of these lines perform different functions, depending on how the user assigns them. Each signal's pin number can be found in Table 3. Table 3. External Signals
Pin BR Signal Name 60x Bus Request Type I/O Description This is an output when an external arbiter is used and an input when an internal arbiter is used. As an output, the PowerQUICC II asserts this pin to request ownership of the 60x bus. As an input, an external master should assert this pin to request 60x bus ownership from the internal arbiter. This is an output when an internal arbiter is used and an input when an internal arbiter is used. As an output, the PowerQUICC II asserts this pin to grant 60x bus ownership to an external bus master. As an input, an external arbiter should assert this pin to grant 60x bus ownership to the PowerQUICC II. As an output the PowerQUICC II asserts this pin for the duration of the address bus tenure. Following an AACK, which terminates the address bus tenure, the PowerQUICC II negates ABB for a fraction of a bus cycle and than stops driving this pin. As an input, the PowerQUICC II will not assume 60x bus ownership, as long as it senses this pin is asserted by an external 60x bus master. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. Assertion of this pin signals the beginning of a new address bus tenure. The PowerQUICC II asserts this signal when one of its internal 60x bus masters (core, dma, PCI bridge) begins an address tenure. When the PowerQUICC II senses this pin being asserted by an external 60x bus master, it will respond to the address bus tenure as required (snoop if enabled, access internal PowerQUICC II resources and memory controller support). When the PowerQUICC II is in the external master bus mode, these pins function as the 60x address bus. The PowerQUICC II drives the address of its internal 60x bus masters and will respond to addresses generated by external 60x bus masters. When the PowerQUICC II is in the internal master bus mode, these pins are used as address lines connected to memory devices and controlled by the PowerQUICC II's memory controller. The 60x bus master drives these pins during the address tenure to specify the type of the transaction. The 60x bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers 4 double words). The 60x bus master drives these pins with a value indicating the amount of bytes transferred in the current transaction. A 60x bus slave asserts this signal to indicate that it has identified the address tenure. Assertion of this signal terminates the address tenure. Assertion of this signal indicates that the bus transaction should be retried by the 60x bus master. The PowerQUICC II asserts this signal to enforce data coherency with its internal cache and to prevent deadlock situations.
BG
60x BusGrant
I/O
ABB IRQ2
60x Address Bus Busy
I/O
Interrupt Request 2 TS T-S 60x Bus Transfer Start
I I/O
A[0:31]
60x Address Bus
I/O
TT[0:4] TBST TSIZ[0:3] AACK ARTRY
60x Bus Transfer Type 60x Bus Transfer Burst 60x Transfer Size 60x Address Acknowledge 60x Address Retry
I/O I/O I/O I/O I/O
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Table 3. External Signals (Continued)
Pin DBG Signal Name 60x Data Bus Grant Type I/O Description This is an output when an internal arbiter is used and an input when an external arbiter is used. As an output, the PowerQUICC II asserts this pin to grant 60x data bus ownership to an external bus master. As an input, the external arbiter should assert this pin to grant 60x data bus ownership to the PowerQUICC II. As an output the PowerQUICC II asserts this pin for the duration of the data bus tenure. Following a TA, which terminates the data bus tenure, the PowerQUICC II negates DBB for a fraction of a bus cycle and then stops driving this pin. As an input, the PowerQUICC II will not assume 60x data bus ownership, as long as it senses this pin is asserted by an external 60x bus master. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. In write transactions, the 60x bus master drives the valid data on this bus. In read transactions, the 60x slave drives the valid data on this bus. The 60x agent that drives the data bus, also drives the data parity signals. The value driven on the data parity 0 pin should provide odd parity (odd number of 1's) on the group of signals that include data parity 0 and D[0:7]. The value driven on this output pin represents the state of the coherency bit in the reservation address register that is used by the Iwarx and stwcx. instructions. An external master should assert this pin to request 60xbus ownership from the internal arbiter. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. The 60x agent that drives the data bus, also drives the data parity signals. The value driven on the data parity 1 pin should provide odd parity (odd number of 1's) on the group of signals that includes data parity 1 and D[8:15]. The PowerQUICC II asserts this pin to grant 60x bus ownership to an external bus master. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. The 60x agent that drives the data bus, also drives the data parity signals. The value driven on the data parity 2 pin should provide odd parity (odd number of 1's) on the group of signals that includes data parity 2 and S[16:23]. This input pin can be used to synchronize 60x core instruction execution to hardware indications. Asserting this pin will force the core to stop instruction execution following a tlbsinc instruction execution. The core resumes instruction execution once this pin is negated. The PowerQUICC II asserts this pin to grant 60x data bus ownership to an external bus master.
DBB IRQ3
60x Data Bus Busy
I/O
Interrupt Request 3 D[0:63] DP[0] RSRV EXT BR2 60x Data Bus 60x Data Parity 0
I I/O I/O
Reservation
O
External Bus Request 2 IRQ1 DP[1] EXT BG2 Interrupt Request 1 60x Data Parity 1
I I I/O
External Bus Grant 2 IRQ2 DP[2] TLBISYNC EXT DBG2 Interrupt Request 2 60x Data Parity 2
O I I/O
TLB Sync:
I
External Data Bus Grant 2
O
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Table 3. External Signals (Continued)
Pin IRQ3 DP[3] CKSTP OUT EXT BR3 Signal Name Interrupt Request 3 60x Data Parity 3 Type I I/O Description This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. The 60x agent that drives the data bus, also drives the data parity signals. The value driven on the data parity 3 pin should provide odd parity (odd number of 1's) on the group of signals that includes data parity 3 and D[24:31]. Assertion of this pin indicates that the core is in its checkstop mode. An external master should assert this pin to request 60x bus ownership from the internal arbiter. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. The 60x agent that drives the data bus, also drives the data parity signals. The value driven on the data parity 4 pin should provide odd parity (odd number of 1's) on the group of signals that includes data parity 4 and D[32:39]. Asserting this pin will force the core to branch to its reset vector. The PowerQUICC II asserts this pin to grant 60x data bus ownership to an external bus master. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. The 60x agent that drives the data bus, also drives the data parity signals. The value driven on the data parity 5 pin should provide odd parity (odd number of 1's) on the group of signals that includes data parity 5 and D[40:47]. This is a count enable input to the Time Base counter in the core. The PowerQUICC II asserts this pin to grant 60x data bus ownership to an external bus master. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. The 60x agent that drives the data bus, also drives the data parity signals. The value driven on the data parity 6 pin should provide odd parity (odd number of 1's) on the group of signals that include data parity 6 and D[48:55]. The cache set entry outputs from the core, represent the cache replacement set element for the current core transaction reloading into, or writing out of, the cache. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. The 60x master or slave that drives the data bus, also drives the data parity signals. The value driven on the data parity 7pin should provide odd parity (odd number of 1's) on the group of signals that include data parity 7 and D[56:63]. The cache set entry outputs from the core, represent the cache replacement set element for the current core transaction reloading into, or writing out of, the cache.
Checkstop Output External Bus Request 3 IRQ4 DP[4] CORE SRESET EXT BG3 Interrupt Request 4 60x Data Parity 4
O I I I/O
Core system reset External Bus Grant 3 IRQ5 DP[5] TBEN EXT DBG3 Interrupt Request 5 60x Data Parity 5
I O I I/O
Time Base Enable External Bus Grant3 IRQ6 DP[6] CSE[0] Interrupt Request 6 60x Data Parity 6
I O I I/O
Cache Set Entry 0
O
IRQ7 DP[7] CSE[1]
Interrupt Request 7 60x Data Parity 7
I I/O
Cache Set Entry 1
O
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Table 3. External Signals (Continued)
Pin PSDVAL Signal Name 60x Data Valid Type I/O Description Assertion of the PSDVAL pin indicates that a data beat is valid on the data bus. The difference between the TA pin and the PSDVAL pin is that the TA pin is asserted to indicate 60x data transfer terminations, while the PSDVAL signal is asserted with each data beat movement. Thus, always when TA is asserted, PSDVAL will be asserted, but, when PSDVAL is asserted, TA is not necessarily asserted. For example, when a double-double word (2x64 bits) transfer is initiated by the SDMA to a memory device that has 32 bits port size, PSDVAL will be asserted 3 times without TA and, finally, both pins will be asserted to terminate the transfer. Assertion of theTA pin indicates that a 60x data beat is valid on the data bus. For 60x single beat transfers, assertion of this pin indicates the termination of the transfer. For 60x burst transfers, this pin will be asserted four times to indicate the transfer of four data beats, with the last assertion indicating the termination of the burst transfer. Assertion of this pin indicates a bus error. 60x masters within the PowerQUICC II monitor the state of this pin. PowerQUICC II's internal bus monitor may assert this pin if it has identified a 60x transfer that is hung. When a 60x master within the chip initiates a bus transaction it drives this pin. When an external 60x master initiates a bus transaction, it should drive this pin. Assertion of this pin indicates that the transfer is global and it should be snooped by caches in the system. The PowerQUICC II data cache monitors the state of this pin. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. This pin is an output pin. It is used for L2 cache control. For each BADDR29 PowerQUICC II 60x transaction initiated in the core, the state of this pin indicates if this transaction should be cached or not. Assertion of the CI pin indicates that the transaction should not be cached. There are five burst address output pins. These pins are outputs of the 60x memory controller. These pins are used in external master configuration and are connected directly to memory devices controlled by PowerQUICC II memory controller. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. Output used for L2 cache control. For each core initiated PowerQUICC II 60x transaction, the state of this pin indicates if the transaction should be cached using write-through or copy-back mode. Assertion of WT indicates that the transaction should be cached using the write-through mode. There are five burst address output pins. These pins are outputs of the 60x memory controller. These pins are used in external master configuration and are connected directly to memory devices controlled by PowerQUICC II's memory controller. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core.
TA
Transfer Acknowledge
I/O
TEA
Transfer Error Acknowledge
I/O
GBL IRQ1
Global
I/O
Interrupt Request 1 CI BADDR29 IRQ2 Cache Inhibit
I O
Burst Address 29
O
Interrupt Request 2 WT BADDR30 IRQ3 Write Through
I O
Burst Address 30
O
Interrupt Request 3
I
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Table 3. External Signals (Continued)
Pin L2 HIT IRQ4 Signal Name L2 Cache Hit Type I Description This pin is used for L2 cache control. Assertion of this pin indicates that the 60x transaction will be handled by the L2 cache. In this case, the memory controller will not start an access to the memory it controls. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. The value of the60x core bus grant is driven on this pin for the BADDR31 use of an external L2 cache. The driven bus grant is non qualified. that is, in the IRQ5 case of external arbiter, the user should qualify this signal with the bus grant input to the PowerQUICC II before connecting it to the L2 Cache. There are five burst address outputs of the 60x memory controller used in the external master configuration and are connected directly to the memory devices controlled by PowerQUICC II's memory controller. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. The value of the 60x core data bus grant is driven on this pin for the use of an external L2 cache. The value of the 60x core bus request is driven on this pin for the use of an external L2 cache. These are output pins that enable specific memory devices or peripherals connected to PowerQUICC II buses. This is an output pin that enables specific memory devices or peripherals connected to PowerQUICC II buses. Output signal whose function is to control buffers on the 60x data bus. This pin will usually be used with BCTL0. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See 6.5.1.8 SIU Module Configuration Register for details. This is an output when the PowerQUICC II is in external arbiter mode and an input when the PowerQUICC II is in internal arbiter mode. When this pin is asserted, the 60x bus arbiter should negate all of its DBG outputs to prevent data bus contention. Output that enables specific memory devices or peripherals connected to PowerQUICC II buses. The 60x master that drives the address bus, also drives the address parity signals. The value driven on address parity 0 pin should provide odd parity (odd number of 1's) on the group of signals that includes address parity 0 and A[0: 7]. There are five burst address output pins. These pins are outputs of the 60x memory controller. Used in external master configuration and connected directly to the memory devices controlled by PowerQUICC II's memory controller. This output pin controls the external address latch that should be used in external master 60x bus configuration. An Output whose function is to control buffers on the 60x data bus. This pin will usually be used with BCTL1 that is MUXed on CS10. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See 6.5.1.8 SIU Module Configuration Register for details.
Interrupt Request 4 CPU BG BADDR31 IRQ5 CPU BusGrant
I O
Burst address 31
O
Interrupt Request 5 CPU DBG CPU BR CS[0:9] CS[10] BCTL1 DBG DIS CPU Bus Data Bus Grant CPU Bus Request Chip Select Chip Select Buffer Control 1
I O O O O O
Data Bus Grant Disable
O
CS[11] AP[0]
Chip Select Address Parity 0
O I/O
BADDR[27:28]
Burst Address 27:28
O
ALE BCTLO
Address Latch Enable Buffer Control 0
O
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Table 3. External Signals (Continued)
Pin PWE[0:7] PSDDQM[0:7] PBS[0:7] Signal Name 60x Bus Write Enable 60x Bus SDRAM DQM 60x Bus UPM Byte Select Type O O O Description Outputs of the 60x bus GPCM, these pins select byte lanes for PSDDQM[0-7] write operations. The DQM pins are outputs of the SDRAM control machine. These pins select specific byte lanes of SRAM devices. The byte select pins are outputs of the UPM in the memory controller. They are used to select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device. An output from the 60x bus SDRAM controller, this pin is part of the address when a row address is driven and is part of the command when a column address is driven. This is one of six general purpose output lines from UPM. The values and timing of this pin are programmed in the UPM; An output from the 60x bus SDRAM controller. This pin should be connected to SRAM's WE input. This is one of six general purpose output lines from UPM. The values and timing of this pin are programmed in the UPM. The output enable pin is an output of the 60x bus GPCM. This pin controls the output buffer of memory devices during read operations. Output from the 60x bus SDRAM controller. This pin should be connected to SDRAM's RAS input. This is one of six general purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. Output from the 60x bus SDRAM controller. This pin should be connected to SDRAM's CAS input. This is one of six general purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. This input pin is used for transaction termination during GPCM operation. This pin requires external pull up resistor for proper operation. This is an input to the UPM. An external device may hold this pin low to force the UPM to wait until the device is ready for the continuation of the operation. This is one of six general purpose output lines from UPM. The values and timing of this pin are programmed in the UPM. In systems in which data parity is stored in a separate chip, this output is used as the byte select for that chip. This output pin controls the 60x SDRAM address multiplexer when the PowerQUICC II is in external master mode. This is one of six general purpose output lines from UPM. The values and timing of this pin are programmed in the UPM.
PSDA10 PGPLO
60x Bus SDRAM A10
O
60x Bus UPM General Purpose Line 0 PSDWE PGPL1 60x Bus SDRAM Write Enable 60x Bus UPM General Purpose Line 1 POE PSDRAS PGPL2 60x Bus Output Enable 60x Bus SDRAM RAS 60xBus UPM General Purpose Line 2. PSDCAS PGPL3 60x bus SDRAM CAS 60x Bus UPM General Purpose line 3 PGTA PUPMWAIT PGPL4 PPBS 60x GPCM TA 60x Bus UPM Wait
O O O O O O O O I I
60x Bus UPM General Purpose Line 4 60 x Bus Parity Byte Select PSDAMUX PGPL5 60x SDRAM Address Multiplexer 60x Bus General Purpose Line 5
O O O O
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Table 3. External Signals (Continued)
Pin LWE[0:3] LSDDQM[0:3] LBS[0:3] Signal Name Local Bus Write Enable Local Bus SDRAM DQM Local Bus UPM byte select Type O O O Description The write enable pins are outputs of the Local bus GPCM. These pins select specific byte lanes for write operations. The DQM pins are outputs of the SDRAM control machine. These pins select specific byte lanes of SDRAM devices. The byte select pins are outputs of the UPM in the memory controller. They are used to select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device. Output from the 60x bus SDRAM controller. This pin is part of the address when a row address is driven and is part of the command when a column address is driven. This is one of six general purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. Output from the local bus SDRAM controller. This pin should be connected to SDRAM's WE input. This is one of six general purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. The output enable pin is an output of the Local bus GPCM. This pin controls the output buffer of memory devices during read operations. Output from the Local bus SDRAM controller. This pin should be connected to the SDRAM RAS input. This is one of six general purpose output lines from UPM. The values and timing of this pin are programmed in the UPM. Output from the Local bus SDRAM controller. This pin should be connected to SDRAM's CAS input. This is one of six general purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. This input pin is used for transaction termination during GPCM operation. This pin requires an external pull up resistor for proper operation. This is an input to the UPM. An external device may hold this pin low to force the UPM to wait until the device is ready for the continuation of the operation. This is one of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM. In systems in which the data parity is stored in a separate chip, this output is used as the byte select for that chip. This is one of six general purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. The local write pin is an output from the local bus memory controller. It is used to distinguish between read and write transactions.
LSDA10 LGPL0
Local Bus SDRAM A10
O
Local Bus UPM General Purpose Line 0 LSDWE LGPL1 Local Bus SDRAM Write Enable Local Bus UPM General Purpose Line 1 LOE LSDRAS LGPL2 Local Bus Output Enable Local Bus SDRAM RAS Local bus UPM General Purpose Line 2 LSDCAS LGPL3 Local Bus SDRAM CAS Local Bus UPM General Purpose Line 3 LGTA LUPWAIT LGPL4 LPBS Local Bus GPCM TA
O O O O O O O O I
Local Bus UPM Wait
I
Local Bus UPM General Purpose Line 4 Local Bus Parity Byte Select LGPL5 LWR Local Bus UPM General Purpose Line 5 Local Write
O O O O
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Table 3. External Signals (Continued)
Pin L_A14 PCI_PAR Signal Name Local Bus Address 14 PCI Parity Type O I/O Description In the local address bus, bit 14 is most significant and bit 31 is least significant. Assertion of this pin indicates that odd parity is driven across AD[31:0] and C/BE3-C/BE0 during address and data phases. Negation of this pin indicates that even parity is driven across the AD31-AD0 and C/BE3C/BE0 signals during address and data phases. In the local address bus, bit 14 FRAME is most significant and bit 31 is least significant. This pin is driven by the PowerQUICC II when its interface is the initiator of a PCI transfer. This pin is asserted to indicate that a PCI transfer is on going. System management interrupt input to the core. In the local address bus, bit 14 is most significant and bit 31 is least significant. This pin is driven by the PowerQUICC II when its PCI interface is the target of a PCI transfer. Assertion of this pin indicates that the PCI target is ready to send or accept a data beat. In the local address bus, bit 14 is most significant and bit 31 is least significant. This pin is driven by the PowerQUICC II when its PCI interface is the initiator of a PC] transfer. Assertion of this pin indicates that the PCI initiator is ready to send or accept a data beat. Assertion of CKSTP_OUT indicates the core is in checkstop mode. In the local address bus, bit 14 is most significant and bit 31 is least significant. This pin is driven by the PowerQUICC II when its PCI interface is the target of a PCI transfer. Assertion of this pin indicates that the PCI target is requesting to stop the PCI transfer. In the local address bus, bit 14 is most significant and bit 31 is least significant. This pin is driven by the PowerQUICC II when its PCI interface is the target of a PCI transfer. Assertion of this pin indicates that a PCI target has recognized a new PCI transfer with an address that belongs to the PCI target. In the local address bus, bit 14 is most significant and bit 31 is least significant. Used to select PowerQUICC II's PCI interface during a PCI configuration cycle. In the local address bus, bit 14 is most significant and bit 31 is least significant. Assertion of this pin indicates that a parity error was detected during a PCI transfer.
L_A15 FRAME SMI
Local Bus Address 15 PCI Frame i
O I/O
System Management Interrupt L-A16 PCI_TRDY Local Bus Address 16 PCI Target Ready
I O I/O
L_A17 PCI_IRDY CKSTP_OUT
Local Bus Address 17 PCI Initiator Ready
O I/O
Checkstop Output L_A18 PCI_STOP Local Bus Address 18 PCI Stop
O O I/O
L_A19 PCI_DEVESEL
Local Bus Address 19 PCI Device Select
O I/O
L_A20 PCI_IDSEL
Local Bus Address 20 PCI ID select
O I O I/O
L_A21 PCI_PERR
Local Bus Address 21 PCI Parity Error
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Table 3. External Signals (Continued)
Pin L_A22 PCI_SERR Signal Name Local Bus Address 22 PCI System Error L_A23 PCI_REQ0 Local Bus Address 23 PCI Arbiter Request 0 Type O I/O O I/O Description In the local address bus, bit 14 is most significant and bit 31 is least significant. Assertion of this pin indicates that a PCI system error was detected during a PCI transfer. In the local address bus, bit 14 is most significant and bit 31 is least significant. When PowerQUICC II's internal PCI arbiter is used, this is an input pin. In this mode assertion of this pin indicates that an external PCI agent is requesting the PCI bus. When an external PCI arbiter is used, this is an output pin. In this mode assertion of this pin indicates that PowerQUICC II's PCI interface is requesting the PCI bus. In the local address bus, bit 14 is most significant and bit 31 is least significant. When PowerQUICC II's internal PCI arbiter is used, assertion of this pin indicates that an external PCI agent is requesting the PCI bus. In the local address bus, bit 14 is most significant and bit 31 is least significant. When PowerQUICC II's internal PCI arbiter is used, this is an output pin. In this mode, assertion of this pin indicates that an external PCI agent that requested the PCI bus with the REQ0 pin is granted the bus. When an external PCI arbiter is used, this is an input pin. In this mode, assertion of this pin indicates that PowerQUICC II's PCI interface is granted the PCI bus. In the local address bus, bit 14 is most significant and bit 31 is least significant. When PowerQUICC II's internal PCI arbiter is used, assertion of this pin indicates that the external PCI agent that requested the PCI bus with the REQ1 pin is granted the bus. In the local address bus, bit 14 is most significant and bit 31 is least significant. In a PCI system where PC8260's PCI interface is configured to operate from an external PCI clock, the 60x bus clock is driven on CLKOUT. In a PCI system where the PC8260's PCI interface is configured to generate the PCI clock, the PCI clock is driven on CLKOUT. The PCI clock frequency range is 25-66MHz. In the local address bus bit 14 is most significant and bit 31 is least significant. When the PC8260 is the host in the PCI system, PCI_RST is an output. When the PC8260is not the host of the PCI system, PCI_RST is an input. This an input to the core. When this input pin is asserted the core branches to its reset vector.
L_A24 PCI_REQ1
Local Bus Address 24 PCI Arbiter Request 1
O I O I/O
L_A25 PCI_GNT0
Local Bus Address 25 PCI Arbiter Grant 0
L_A26 PCI_GNT1
Local Bus Address 26 PCI Arbiter Grant 1
O O
L_A27 CLKOUT
Local Bus Address 27 Clock Output pin
O O
L_A28 PCI_RST CORE_SRESET
Local Bus Address 28 PCI Reset
O I/O
Core System Reset
I
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Table 3. External Signals (Continued)
Pin L_A29 PCI_INTA Signal Name Local Bus Address 29 PCI INTA Type O I/O Description In the local address bus, bit 14 is most significant and bit 31 is least significant. When the PowerQUICC II is the host in the PCI system, this pin is an input for delivering PCI interrupts to the host. When the PowerQUICC II is not the host of the PCI system, this pin is an output used by the PowerQUICC II to signal an interrupt to the PCI host. In the local address bus, bit 14 is most significant and bit 31 is least significant. In the local address bus, bit 14 is most significant and bit 31 is least significant. DLLSYNC is used to eliminate skew for the clock driven on CLKOUT. In the local data bus, bit 0 is most significant and bit 31 is least significant. PCI bus address data input/output pins. In the PCI address data bus, bit 31 is most significant and bit 0 is least significant. In local bus write operations the PowerQUICC II drives these pins. In local bus read operations the accessed device drives these pins. LCL_DP(0) is driven with a value that gives odd parity with LCL_D(0:7). LCL-DP(1) is driven with a value that gives odd parity with LCL_D(8:15). LCL_DP(2) is driven with a value that gives odd parity with LCL_D(16:23). LCL_DP(3) is driven with a value that gives odd parity with LCL_D(24:31) The PowerQUICC II drives these pins when it is the initiator of a PCI transfer. This input is one of the eight external lines that can request (by means of the NMI-OUT internal interrupt controller) a service routine from the core. This is an output driven from PowerQUICC II's internal interrupt controller. Assertion of this output indicates that an unmasked interrupt is pending in PowerQUICC II's internal interrupt controller. This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. This is an output driven from PowerQUICC II's internal interrupt controller. Assertion of this output indicates that an unmasked interrupt is pending in PowerQUICC II's internal interrupt controller. This output pin will be asserted when the PowerQUICC II's detects wrong parity driven on its address parity pins by an external master This is the reset input to PowerQUICC II's JTAG/COP controller. This pin provides the clock input for PowerQUICC II's JTAG/COP controller. This pin controls the state of PowerQUICC II's JTAG/COP controller. This pin is the data input to PowerQUICC II's JTAG/COP controller. This pin is the data output from PowerQUICC II's JTAG/COP controller.
L_A30 L_A31 DLLSYNC
Local Bus Address 30 Local Bus Address 31 DLL Synchronization
O O I I/O I/O I/O
LCL_D[0:31] PCI_AD[0:31]
Local Bus Data PCI Address Data
LCL_DP[0:3] PCI_C/BE[0:3]
Local Bus Data Parity
PCP Command/Byte Enable IRQ0 NMI_OUT Interrupt request 0
I/O I
Non Maskable Interrupt Output IRQ7 INT_OUT APE Interrupt Request 7 Interrupt Output
O
I O
Address Parity Error TRST TCK TMS TDI TDO Test Reset (JTAG) Test Clock (JTAG) Test Mode Select (JTAG) Test Data In (JTAG) Test Data Out (JTAG)
O I I I I O
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Table 3. External Signals (Continued)
Pin TRIS PORESET HRESET SRESET QREQ Signal Name Three State Power-on Reset Hard Reset Soft Reset Quiescent Request Type I I I/O I/O O Description Asserting TRIS forces all other PowerQUICC II's pins to high impedance state. When asserted, this input line causes the PowerQUICC II to enter power-on reset state. This open drain line, when asserted, causes the PowerQUICC II to enter hard reset state. This open drain line, when asserted, causes the PowerQUICC II to enter soft reset state. This pin indicates that PowerQUICC II's internal core is about to enter its low power mode. In the PowerQUICC II, this pin will be typically used for debug purposes. This input lien is sampled by the PowerQUICC II during the assertion of the HRESET signal. If the line is asserted, the configuration mode is sampled in the form of the hard reset configuration word driven on the data bus. When this line is negated, the default configuration mode is adopted by the PowerQUICC II. Notice that the initial base address of internal registers is determined in this sequence. Defines the operating mode of internal clock circuits. The 60x master that drives the address bus, also drives the address parity signals. The value driven on the address parity 1 pin should provide odd parity (odd number of 1's) on the group of signals that includes address parity 1 and [A8:15]. The transfer code output pins supply information that can be useful for debug purposes for each of the PowerQUICC II initiated bus transactions. The bank select outputs are used for selecting SDRAM bank when the PowerQUICC II is in 60x compatible bus mode. Defines the operating mode of internal clock circuits. The 60x master that drives the address bus, also drives the address parity signals. The value driven on the address parity 2 pin should provide odd parity (odd number of 1's) on the group of signals that includes address parity 2 and [A16:23]. The transfer code output pins supply information that can be useful for debug purposes for each of the PowerQUICC II initiated bus transactions. The bank select outputs are used for selecting SDRAM bank when the PowerQUICC II is in 60x compatible bus mode.
RSTCONF
Reset Configuration
I
MODCK1 AP[1] TC[0] BNKSEL[0]
Clock Mode Input Address Parity 1
I I/O
Transfer Code 0
O
Bank Select 0 MODCK2 AP[2] TC[1] BNKSEL[1] Clock Mode Input Address Parity 2
O I I/O
Transfer Code 1
O
Bank Select 1
O
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Table 3. External Signals (Continued)
Pin MODCK3 AP[3] TC[2] BNKSEL[2] Signal Name Clock Mode Input Address Parity 3 Type I I/O Description Defines the operating mode of internal clock circuits. The 60x master that drives the address bus, also drives the address parity signals. The value driven on the address parity 3 pin should provide odd parity (odd number of 1's) on the group of signals that includes address parity 3and [A24:314]. The transfer code output pins supply information that can be useful for debug purposes for each of the PowerQUICC II initiated bus transactions. The bank select outputs are used for selecting SDRAM bank when the PowerQUICC II is in 60x compatible bus mode. Input connection for an external capacitor filter for PLL circuity. Primary clock input to PowerQUICC II's PLL. General Purpose I/O Port General Purpose I/O Port General Purpose I/O Port General Purpose I/O Port Power supply of the internal logic Power supply of the I/O buffers Power supply of the PLL circuity Special ground of the PLL circuity Power supply of the core's PLL circuity
Transfer Code 2
O
Bank Select 2 XFC CLKIN PA[0:31] PB[4:31] PC[0:31] PD[4:31] VDD VDDH VCCSYN GNDSYN VCCSYN1 External Filter Capacitance Clock In Port A Bits 0:31 Port B Bits 4:31 Port C Bits 0:31 Port D Bits 4:31 Power Supply Power Supply Power Supply Special Ground Power Supply
O I I I/O I/O I/O I/O
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Applicable Documents Requirements
General Terminal Connections Absolute Maximum Ratings Table 4. Maximum Ratings
Symbol VDD VCCSYN VDDH VIN TSTG Note: Rating Core Supply Voltage PLL Supply Voltage I/O Supply Voltage Input Voltage Storage Temperature Range Value -0.3/2.75 -0.3/2.75 -0.3/3.6 (GND-0.3)/3.6 -65/+150 Unit V V V V C
1. MIL-STD-883: Test methods and procedures for electronics. 2. SQ32S0100.0: Quality levels for supplied components.
The microcircuits are in accordance with the applicable documents and as specified herein. The terminal connections are shown in Table 2 on page 8.
Absolute maximum ratings are stress ratings only. Functional operation (see Table on page 34) at the maximums is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.
Warning
VIN must not exceed VDDH by more than 2.5V at any time, including during power-on reset. VDDH must not exceed VDD/VCCSYN by more than 1.6V at any time, including during power-on reset. V DD/V CCSYN must not exceed V DDH by more than 0.4V at any time, including during power-on reset. It is recommended to use a bootstrap diode between the power rails, as shown in Figure 3. Figure 3. Bootstrap Diodes for Power-up Sequencing
I/O Power MUR420 MUR420 Core/Pll Power
3.3V (VDDH)
2.5V(VDD/VCCSYN)
Select the bootstrap diodes so that a nominal VDD/VCCSYN is sourced from the VDDH power supply until the VDD/VCCSYN power supply becomes active. In Figure 3, two MUR420 Schottky barrier diodes are connected in a series; each has a forward voltage (VF) of 0.6V at high currents, and so provides a 1.2V drop, maintaining 2.1V on the 2.5V power line. Once the core/PLL power supply stabilizes at 2.5V, the bootstrap diode(s) will be reverse biased with negligible leakage current. The forward voltage should be effective at the current levels needed by the processor, approximately 2-3 amps. That is, do not use diodes with only a nominal VF which drops too low at high current.
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Recommended Operating Conditions Table 5. Recommended Operational Voltage Conditions
Symbol Rating Core Supply Voltage PLL Supply Voltage I/O Supply Voltage Input Voltage Junction Temperature 2.5V Device 2.4 / 2.7 2.4 / 2.7 3.15 / 3.465 GND -0.3 / 3.6 -55 / + 125 Unit V V V V C
VDD
VCCSYN
VDDH
VIN TJ Note:
The recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
This device contains circuitry to protect against damage due to high static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or VCC).
Table 6. Thermal Characteristics
Symbol JA JA JA JA Notes: Characteristics Thermal Resistance for TBGA Value 13.5
(1)
Unit C/W C/W C/W C/W
Air Flow NC(2) 1 m/s NC 1 m/s
11.0(1) 10.8(3) 8.5 1. Assumes a single layer board with no thermal bias 2. Natural convection 3. Assumes a four layer board
(3)
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Power Considerations The average chip-junction temperature, TJ, in C can be obtained from the following:
T J = T A + ( P D * JA )
where
(1)
TA = ambient temperature C QJA = package thermal resistance, junction to ambient, C/W PD = PINT + PI/O PINT =IDD x VDD Watts-chip internal power PI/O = power dissipation on input and output pins-user determined
P I O < 0.3 * P INT
Can be neglected for most applications. If P I/O is neglected, an approximate relationship between PD and TJ is the following: PD = K / (TJ + 273 C) (2) (3)
Solving equations (1) and (2) for K gives:
K = P D * ( T A + 273C ) + * P D 2
Where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. Layout Practices Each VCC pin on the PC8260 should be provided with a low-impedance path to the board's power supply. Each ground pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1 F by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC and ground should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the PC8260 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data busses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
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Electrical Characteristics
DC Electrical Specification This section describes the DC electrical characteristics for the PC8260. The measurements in Table 7 assume the following system conditions: TC = -55C to +125C VDD = 2.0 5% VDC VDDH = 3.3 5% VDC GND = 0 VDC The leakage current is measured for nominal VDDH and VDD, or both. VDDH and VDD must vary in the same direction (for example, both VDDH and VDD vary by either +5% or -5%). Table 7. DC Electrical Characteristics
Symbol VIH VIL VIHC VILC IIN IOZ IL IH VOH Characteristic Input High Voltage, All Inputs Except CLKIN Input Low Voltage CLKIN Input High Voltage CLKIN Input Low Voltage Input Leakage Current, VIN= VDDH Hi-Z (off state) Leakage Current, VIN = VDDH Signal Low Input Current, VIL= 0.8V Signal High Input Current, VIH = 2.0V Output High Voltage, IOH = -2 mA Except XFC, and Open Drain Pins TBD TBD 2.4 Min 2.0 GND 2.4 GND Max 3.465 0.8 3.465 0.4 10 10 TBD TBD Unit V V V V A A A A V
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Table 7. DC Electrical Characteristics (Continued)
Symbol VOL Characteristic IOL = 7.0 mA BR BG ABB/IRQ2 TS A[0:31] TT[0:4] TBST TSIZE[0:3] AACK ARTRY DBG DBB/IRQ3 D[0:63] DP(0)/RSRV DP(1)/IRQ1 DP(2)/TLBISYNC/IRQ2 DP(3)/IRQ3 DP(4)/IRQ4 DP(5)/TBEN/IRQ5 DP(6)/CSE(0)/IRQ6 DP(7)/CSE(1)/IRQ7 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR IRQ0/NMI_OUT IRQ7/INT_OUT/APE PORESET SRESET RSTCONF QREQ Min Max 0.4 Unit V
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Table 7. DC Electrical Characteristics (Continued)
Symbol VOL Characteristic IOL = 5.3 mA CS[0:9] CS(10)/BCTL1 CS(11)/AP(0) BADDR[27-28] ALE BCTL0 PWE(0:7)/PSDDQM(0:7)/PBS(0:7) PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE[0-3]LSDDQM(0:3)/LBS([0-3] LSDA10/LGPL0 LSDWE/LGPL1 LOE/LSDRAS/LGPL2 LSDCAS/LGPL3 LGTA/LUPMWAIT/LGPL4/LPBS LGPL5 LWR MODCK1/AP(1)/TC(0)/BNKSEL(0) MODCK2/AP(2)/TC(1)/BNKSEL(1) MODCK3/AP(3)/TC(2)/BNKSEL(2) IOL = 3.2 mA L_A14 L_A15/SMI L_A16 L_A17/CKSTP_OUT L_A18 L_A19 L_A20 L_A21 L_A22 L_A23 L_A24 L_A25 L_A26 L_A27 L_A28/CORE_SRESET Min Max 0.4 Unit V
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Table 7. DC Electrical Characteristics (Continued)
Symbol VOL Characteristic L_A29 L_A30 L_A31 LCL_D(0:31) LCL_DP(0:3) PA[0:31] PB[4:31] PC[0:31] PD[4:31] TDO Min Max 0.4 Unit V
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AC Electrical Specifications
Included in this section are illustrations and tables of clock diagrams, signals, and CPM outputs and inputs. Note that AC timings are based on a 50 pF load. Typical output buffer impedances are shown in Table 8.
Table 8. Output Buffer Impedances
Output Buffers 60x bus Local bus Memory Controller Parallel I/O PCI Note: Typical Impedance () 40 40 40 46 25 These are typical values at 65C. The impedance may vary by 25% with process and temperature.
Although the specifications generally refer to the rising edge of the clock, the following AC timing diagrams also apply when the falling edge is the active edge. Figure 4. FCC External Clock Diagram
Serial CLKin
sp17b FCC Input Signals sp16b
sp36b/sp37b FCC Output Signals
Figure 5. FCC Internal Clock Diagram
sp17a BRG_OUT
FCC Input Signals
sp16a
sp36a/sp37a FCC Output Signals
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Figure 6. SCC/SMCSPI/I2C External Clock
Serial CLKin sp19b sp18 SCC/SMCSPI/I2C Input Signals sp38b/sp39b SCC/SMCSPI/I2C Output Signals
Figure 7. SCC/SMC/SPI/I2C Internal Clock Diagram
BRG_OUT
sp18a SCC/SMC/SPI/I2C Input Signals
sp19a
sp38a/sp39a SCC/SMC/SPI/I2C Output Signals
Figure 8. PIO, Timer and DMA Signal Diagram
CLKin
sp23 PIO/TIMER/DMA Input Signals sp22
sp42/sp43 PIO/TIMER/DMA Output Signals
sp42 PIO Output Signals
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Figure 9. TDM Signal Diagram
Serial CLKin sp20 TDM Input Signals sp21
sp40/sp41 TDM Output Signals
Table 9. AC Characteristics for CPM Outputs
Spec_num sp36a/sp37a sp36b/sp37b sp40/sp41 sp38a/sp39a sp38b/sp39b sp42/sp43 Note: Characteristics FCC Outputs - Internal clock (NMSI) FCC Outputs - External clock (NMSI) TDM Outputs SCC/SMC/SPI/I2C Outputs - Internal Clock (NMSI) EX_SCC/SMC/SPI/I2C Outputs - External Clock (NMSI) PIO/TIMER/DMA Outputs Max Delay (ns) 6 18 35 20 30 14 Min Delay (ns) 0 2 5 0 0 1
Output specifications are measured from the 1.4V level of the rising edge of CLKIN to the TTL level (0.8 or 2.0V) of the signal. Timing is measured at the pin.
Table 10. AC Characteristics for CPM Inputs
Spec_num sp16a/sp17a sp16b/sp17b sp20/sp21 sp18a/sp19a sp18b/sp19b sp22/sp23 Note: Characteristics FCC Inputs - Internal clock (NMSI) FCC Inputs - External clock (NMSI) TDM Inputs ISCC/SMC/SPI/I2C Inputs - Internal Clock (NMSI) SCC/SMC/SPI/I2C Inputs - External Clock (NMSI) PIO/TIMER/DMA Outputs Setup (ns) 10 5 20 20 5 10 Hold (ns) 0 3 20 0 5 3
Input specifications are measured from the TTL level (0.8 or 2.0V) of the signal to the 1.4 level of the rising edge of CLKIN. Timing is measured at the pin.
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Figure 10. Interaction of Bus Signals
CLKin sp11
AACK/ARTRY/TA/TEA/DBG/BG/BR Input Signals
sp10
sp12 Data Bus Name Input Signal
sp10
sp15 All Other Input Signals
sp10
sp31/sp30 PSDVAL/TEA/TA Output Signals sp32/sp30 ADD/ADD_atr/BADDR/CI/GBL/WT Output Signals sp33a/sp30 DATA Bus Output Signals sp35/sp30 All Other Output Signals
Figure 11. ECC Mode Diagram
sp10
sp10 sp13 DATA Bus, ECC, and PARITY Mode Input Signals
sp10 sp14 DP Mode Input Signal
DP Mode Output Signal
sp33b/sp30
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Figure 12. MEMC Mode Diagram
CLKin
V_CLK
Memory Controller Signals
sp34/sp30
Table 11. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin) PLL Clock Radio 1:2, 1:3, 1:4, 1:5, 1:6 1:2.5 1:3.5 Note: T2 1/4 CLKin 3/10 CLKin 4/14 CLKin T3 1/2 CLKin 1/2 CLKin 1/2 CLKin T4 3/4 CLKin 8/10 CLKin 11/14 CLKin
Generally, all PC8260 bus and system output signals are driven from the rising edge of the input clock (CLKin). Memory controller signals, however, trigger on four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of CLKin (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as shown in Table 11.
Figure 13. Internal Tick Spacing for Memory Controller Signals
CLKin T1 T2 T3 T4 for 1:2, 1:3, 1:4, 1:5, 1:6
CLKin T1 T2 T3 T4
for 1:2.5
CLKin T1 T2 T3 T4
for 1:3.5
Note:
The UPM machine and GPCM machine outputs change on the internal tick determined by the memory controller programming. The AC specifications are relative to the internal tick. Note that SDRAM machine outputs change only on the CLKin's rising edge.
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Table 12. AC Characteristics for SIU Inputs
Spec_num sp11/sp10 sp12/sp10 sp13sp10 sp14/sp10 sp15/sp10 Notes: Characteristics AACK/ARTRY/TA/TEA/DBG/BG/BR Data Bus in Normal mode Data Bus in ECC and PARITY Modes DP pins All Other Pins Setup (ns) 6 5 8 8 5 Hold (ns) 1 1 1 1 1
1. Input specifications are measured from TTL level (0.8 or 2.0V) of the signal to the 1.4 level of the rising edge of CLKIN. 2. Timings are measured at the pins.
Table 13. AC Characteristics for SIU Outputs
Spec_num sp31/sp30 sp32/sp30 sp33a/sp30 sp33b/sp30 sp34/sp10 sp35/sp10 Notes: Characteristics PSDVAL/TEA/TA ADD/ADD_atr./BADDR/CIGBL/WT Data Bus DP Memc Signals/ALE All Other Signals Max Delay (ns) 10 8 8 12 6 7 Min Delay (ns) 1 1 1 1 1 1
1. Output specifications are measured from the 1.4V level of the rising edge of CLKIN to the TTL level (0.8 or 2.0V) of the signal. 2. Timings are measured at the pin.
Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC timing. When data pipelining is activated, sp12 can be used for data bus setup even when ECC or PARITY are used. Also, sp33a can be used as the AC specification for DP signals.
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Clock Configuration Modes
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the MODCK[1:3] pins are sampled while HRESET is asserted. Table 14 shows the eight basic configuration modes. Another 49 modes are available by using the configuration pin (RSTCONF) and driving four pins on the data bus.
Table 14. Clock Default Modes
Input Clock Frequency (MH)z 33 33 33 33 66 66 66 66 CPM Multiplication Factor 3 3 4 4 2 2 2.5 2.5 CPM Frequency (MHz) 100 100 133 133 133 133 166 166 Core Multiplication Factor 4 5 4 5 2.5 3 2.5 3 Core Frequency (MHz) 133 166 133 166 166 200 166 200
MODCK[1-3] 000 001 010 011 100 101 110 111
Table 15. Clock Configuration Modes
MODCK_H- MODCK[1-3] 0001_000 0001_001 0001_010 0001_011 0001_100 Input Clock Frequency (MHz) 33 33 33 33 33 CPM Multiplication Factor 2 2 2 2 2 CPM Frequency (MHz) 66 66 66 66 66 Core Frequency (MHz) 133 166 200 233 266
Core Multiplication Factor 4 5 6 7 8
0001_101 0001_110 0001_111 0010_000 0010_001
33 33 33 33 33
3 3 3 3 3
100 100 100 100 100
4 5 6 7 8
133 166 200 233 266
0010_010 0010_011 0010_100 0010_101 0010_110
33 33 33 33 33
4 4 4 4 4
133 133 133 133 133
4 5 6 7 8
133 166 200 233 266
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Table 15. Clock Configuration Modes (Continued)
MODCK_H- MODCK[1-3] 0010_111 0011_000 0011_001 0011_010 0011_011 Input Clock Frequency (MHz) 33 33 33 33 33 CPM Multiplication Factor 5 5 5 5 5 CPM Frequency (MHz) 166 166 166 166 166 Core Frequency (MHz) 133 166 200 233 266
Core Multiplication Factor 4 5 6 7 8
0011_100 0011_101 0011_110 0011_111 0100_000
33 33 33 33 33
6 6 6 6 6
200 200 200 200 200
4 5 6 7 8
133 166 200 233 266 MHz
0100_001 0100_010 0100_011 0100_100 0100_101 0100_110
Reserved
0100_111 0101_000 0101_001 0101_010 0101_011 0101_100
Reserved
0101_101 0101_110 0101_111 0110_000 0110_001 0110_010
66 66 66 66 66 66
2 2 2 2 2 2
133 133 133 133 133 133
2 2.5 3 3.5 4 4.5
133 166 200 233 266 300
0110_011 0110_100
66 66
2.5 2.5
166 166
2 2.5
133 166
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Table 15. Clock Configuration Modes (Continued)
MODCK_H- MODCK[1-3] 0110_101 0110_110 0110_111 0111_000 Input Clock Frequency (MHz) 66 66 66 66 CPM Multiplication Factor 2.5 2.5 2.5 2.5 CPM Frequency (MHz) 166 166 166 166 Core Frequency (MHz) 200 233 266 300
Core Multiplication Factor 3 3.5 4 4.5
0111_001 0111_010 0110_101 0110_110 0110_111 0111_000
66 66 66 66 66 66
3 3 2.5 2.5 2.5 2.5
200 200 166 166 166 166
2 2.5 3 3.5 4 4.5
133 166 200 233 266 300
0111_001 0111_010 0111_011 0111_100 0111_101 0111_110 0111_111 1000_000 1000_001 1000_010 1000_011 1000_100 Notes:
66 66 66 66 66 66 66 66 66 66 66 66
3 3 3 3 3 3 3.5 3.5 3.5 3.5 3.5 3.5
200 200 200 200 200 200 233 233 233 233 233 233
2 2.5 3 3.5 4 4.5 2 2.5 3 3.5 4 4.5
133 166 200 233 266 300 133 166 200 233 266 300
1. This table describes all possible clock configurations when using the hard reset configuration sequence. Note that clock configuration changes only after POR is asserted. 2. Because of speed dependencies, not all of the possible configurations in this table may be applicable. 3. The 66 MHz configurations are required for input clock frequencies higher than 50 MHz. 33 MHz configurations are required for input clock frequencies below 50 MHz. 4. The user should choose the input clock frequency, and the multiplication factor of the CPM so that the frequency of the CPM will be between 50 MHz and 166 MHz for a 2V part, and between 66 MHz and 233 MHz for a 2.5V part.
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PC8260 PowerQUICC II
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PC8260 PowerQUICC II
Status
Table 16. Datasheet Status
Datasheet Status Objective Specification Target Specification Preliminary Specification Site This datasheet contains target and goal specification for discussion with customer and application validation. This datasheet contains target or goal specifications for product development. This datasheet contains preliminary data. Additional data may be published later. This could include simulation results. This datasheet also contains characterization results. This datasheet contains final product specifications. Validity Valid before design phase
Valid during the design phase
Valid before the characterization phase Valid before the industrialization phase. Valid for production purposes
Preliminary Specification Site Product Specification
Limiting Values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Where application information is given, it is advisory and does not form part of the specification. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. ATMELGrenoble customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel-Grenoble for any damages resulting from such improper use or sale.
Application Information Life Support Applications
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2131A-08/01
Package Dimensions TBGA480
F
CORNER
B
E 0.150 T
T
A1 INDEX A B C
A
MIN
MAX
37.5 BSC 37.5 BSC 1.45 0.65 0.85 0.50 1.65 0.85 0.95 0.70
D G H K L 4X
Top View
1.27 BSC 35.56 BSC
0.2
28 26 24 22 20 18 16 14 12 10 8 6 4 2 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 A C E G J L N R U W B D F H K M P T V K
Y AA AB AC AD AE AF AG AH AJ Bottom View C G H L
480X D K
All measurements are in mm.
Notes: 1. Dimensions and tolerancing per asme Y14.5M-1994. 2. Dimensions in millimeters. 3. Dimension b is measured at the maximum solder ball diameter. Parallel to primary datum A. 4. Primary datum A and the seating plane are defined by the spherical crowns of the solder balls.
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PC8260 PowerQUICC II
2131A-08/01
PC8260 PowerQUICC II
Ordering Information
Revision A1
PC (X) 8260 M TP U 200 (A1 ) Revision Level
Prefix
(1)
Prototype Type Temperature Range: Tj M: V: -55, +125 C -40, +110 C
Max. Internal Processor Speed
(2)
Package TP: TBGA
200/200 MHz 150/150 MHz
Screening Level U: Upscreening
(2)
(1) Atmel-Grenoble (2) For availability of the different versions, contact your sales office.
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2131A-08/01
Revision B1 and Above
PC (X)
8260
M TP
U
IFB
B1
Revision Level
Prefix
(1)
Prototype Core Voltage Type Temperature Range: Tj M: V: -55, +125 C -40, +110 C = 2.5 V + 0.2, -0.1 Volt V = 1.8 V 0.1 Volt
CPU/CPM/Bus Speed (MHz) A = 50, B = 66, C= 75 D = 83, E = 100, F = 133 G = 150, H = 166, I = 200 J = 233, K = 266, L = 300 M = 333
Package: TP: TBGA
Screening Level U: Upscreening
(2)
(1) Atmel-Grenoble (2) For availability of the different versions, contact your sales office.
52
PC8260 PowerQUICC II
2131A-08/01
Atmel Headquarters
Corporate Headquarters
2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600
Atmel Product Operations
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Asia
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Japan
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Atmel Smart Card ICs
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e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
(c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Atmel(R) is the registered trademark of Atmel. PowerQUICCII TMand PC603e TMare the trademarks of Atmel. PowerPC TM is a trademark of IBM Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper.
2131A-08/01/0M

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